The present invention pertains to the controlling of one or more components coupled to a bus. More particularly, the present invention pertains to the changing of operation of a component coupled to a bus in dependence on the bus clock frequency.
In a computer architecture, a processor (e.g. a Pentium®-II processor, Intel Corporation, Santa Clara, Calif.) is typically coupled to a main circuit board (also referred to as a motherboard). The motherboard typically includes electrically conductive traces that allow the processor to be coupled to a variety of components. An example of a computer architecture can be found in the Intel publication “Peripheral Components,” pp. 1–9 to 1–10, 1996 (available from McGraw-Hill Book Company). In that architecture, the processor is coupled to a host bus which couples the processor to several “local” components, such as an additional processor, a memory input/output (I/O) controller, and a Host-to-PCI bridge circuit. The Host-to-PCI bridge circuit (e.g., as part of the 82430FX PCIset from Intel Corporation) provides an interface between the host bus and a peripheral component interconnect (PCI) bus (Rev. 2.1, PCI Special Interest Group, Hillsboro, Oreg., 1995). The PCI bus is typically coupled to a number of performance critical devices (i.e., devices that require a fast data throughput) such as a graphics controller and PCI-to-ISA bridge circuit (also provided in the 82430FX PCIset). An Industry Standard Architecture (ISA) bus is typically coupled to devices that are not performance critical such as a standard floppy drive or hard-disc drive.
Devices coupled to the host, PCI, and ISA busses are typically synchronous devices in that they assert signals and receive signals to/from these busses at specific times with reference to a periodic bus clock. For example, a host bus clock source is coupled to each device that is coupled to the host bus. This host bus clock typically runs at a frequency of 60 MegaHertz (MHZ—one million cycles per second) or 66 MHZ. One skilled in the art will appreciate that a clocking signal with a frequency lower than these frequencies can be supplied to the devices, where the devices increase (e.g., through multiplication) the frequency to the desired operating frequency. The internal clock of the processor typically runs at a multiple of the host bus clock frequency. For example, a 200 MHZ Pentium® Pro processor runs at approximately three times the host bus clock frequency of 66 MHZ.
According to the Pentium® Pro Processor Specification (Pentium® Pro Family Developer's Manual, Volume 1: Specifications, 1996, available from Intel Corporation), there is a specific protocol for sending data over the host bus between bus devices. For example, when a device (e.g., a Pentium® Pro processor) seeks to send data onto the host bus to be read by another device (e.g., a memory I/O controller) it must assert (or drive) the signal(s) (e.g., control, address, and/or data signals) onto the bus during a specific time window. With a host bus speed of 66 MHZ, the signal(s) must be driven onto the host bus no earlier than a time tco-min (e.g., 1.0 nanoseconds) after the rising edge of a bus clock cycle and no later than tco-max (e.g., 4.5 ns) after the rising edge of a bus cycle. In receiving the signal from the bus, the receiving device must look for and latch the signal during a second time window which is defined as tsetup (e.g., 2.5 ns) before the rising edge of the next bus clock cycle and thold (e.g., 0.0 ns) after this same rising edge.
To improve performance of the overall system architecture, it would be desirable to increase the frequency of the host bus clock, thus increasing the amount (per unit of time) of control, address, and data signals that can be driven and received onto/from the host bus. For example, at a bus speed of 100 MHZ, approximately 50% more of such signals can be transferred over the host bus when compared to 66 MHZ. There are several problems that can occur by unilaterally increasing the host bus clock. For example, in doing so, it is possible that the receiving device will not be able to latch the signal sent to it over the bus, given the timing window limitations present in the specification. This is due, in part, to the limitations of electronic circuits (e.g., switching times) in these devices and clock skew perceived by the sending and receiving devices. Because many computer architectures comprise components that can be removed and replaced, it is possible that a user may attempt to increase the clocking frequency of the host bus after the processor has been updated to a faster operating speed.
In view of the foregoing problems with increasing bus clock speeds, there is a need for a method and apparatus that allows devices to effectively communicate with a bus at multiple bus clock frequencies.